1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit in an apparatus for reproducing information recorded on a recording medium.
2. Description of the Related Background Art
A Viterbi decoding (Viterbi Algorithm) is known as a method whereby recording information recorded on a recording medium at a high density is decoded with high reliability. In the Viterbi decoding, a read signal read from the recording medium is not judged as a binary of "1" or "0" on the basis of a predetermined threshold value but sampling values obtained by sampling the read signal are handled as a continuous time sequence and a data train which seems to be certain is obtained on the basis of the time sequence. In a recording information reproducing apparatus using the Viterbi decoding, sampling data sampled by a reproduction clock signal having a predetermined relative phase which follows to a time base fluctuation of the read signal is needed.
FIG. 1 is a diagram Showing an example of a construction of the recording information reproducing apparatus using the Viterbi decoding.
In FIG. 1, a recording disk 3 on which information has been recorded is rotated by a spindle motor 2. A pickup 1 reads the recorded information on the recording disk 3 and generates a read signal to supply it to a head amplifier 4. The head amplifier 4 supplies an amplified read signal obtained by properly amplifying the supplied read signal to each of an A/D converter 5 and a sync detecting circuit 6. The sync detecting circuit 6 detects a sync signal from the amplified read signal, generates a sync detection signal at the time point of the detection, and supplies the sync detection signal to a spindle servo circuit 7. A frequency dividing circuit 8 generates a reference frequency dividing clock signal obtained by dividing a reference clock signal having a predetermined frequency supplied from a reference clock generating circuit 9 to a specified frequency of the sync signal and supplies the reference frequency dividing clock signal to the spindle servo circuit 7. The spindle servo circuit 7 obtains a frequency difference between the frequency of the reference frequency dividing clock signal and the frequency of the sync detection signal and supplies it as a frequency error signal to the spindle motor 2. The spindle servo circuit 7 further obtains a phase difference between the phase of the reference frequency dividing clock signal and the phase of the sync detection signal and supplies it as a phase error signal to the spindle motor 2. The spindle motor 2 rotates the recording disk 3 at a rotational speed based on the frequency error signal and the phase error signal.
The A/D converter 5 sequentially converts the amplified read signal amplified by the head amplifier 4 to a sampled value at a timing of a reproduction clock signal supplied from a PLL circuit 10 and supplies the sampled value to each of the PLL circuit 10 and a time base correcting circuit 20.
The time base correcting circuit 20 is constructed by, for example, a FIFO (First-In First-Out) memory. The circuit 20 sequentially writes the sampled value supplied from the A/D converter 5 at a timing of the reproduction clock signal, further sequentially reads the sampled value at a timing of the reference clock signal, and supplies it to a Viterbi decoder 30. A time base fluctuation component in association with the rotation of the recording disk 3 is eliminated by the operation of the time base correcting circuit 20. The Viterbi decoder 30 handles the sampled value whose time base was corrected by the time base correcting circuit 20 as a continuous time sequence and obtains reproduced data which seems to be certain on the basis of the time sequence.
A phase detecting circuit 11 in the PLL circuit 10 detects the phase error occurring in the read signal on the basis of a sampled value sequence which is sequentially supplied from the A/D converter 5 and supplies the phase error signal corresponding to the phase error component to a D/A converter 12. The D/A converter 12 supplies a phase error voltage value obtained by converting the phase error signal to a voltage value corresponding to the phase error signal to an LPF (low pass filter) 13. The LPF 13 supplies an average phase error voltage value obtained by averaging the phase error voltage values to a VCO (voltage controlled oscillator) 14. The VCO 14 generates a clock signal having an oscillating frequency corresponding to the average phase error voltage value and supplies the clock signal as a reproduction clock signal to each of the A/D converter 5 and the time base correcting circuit 20.
As mentioned above, the reproduction clock signal whose frequency changes so as to correct the phase error occurring in the read signal can be obtained by the PLL circuit 10. The A/D converter 5, therefore, can sequentially generate the sampling value at a timing having a fixed relative phase which follows the time base fluctuation of the read signal.
In the PLL circuit 10, however, since the VCO with an analog circuit construction for generating the clock signal of an oscillating frequency corresponding to an input voltage value is used, the circuit is easily influenced by a fluctuation of a power source voltage, an ambient temperature, an aging change in characteristics, and the like, so that there is a problem such that stable loop characteristics cannot be obtained. Since the VCO with the analog circuit construction has errors and a variation of circuit element values, further, there is a problem such that it is necessary to adjust the oscillating frequency.